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1 7829a?aero?10/08 features ? also known as smcs116spw ? single bidirectional spacewire link allowing ? full duplex communication ? transmit rate from 1.25 up to 200 mbit/s in each d irection ? supports serial transfer universal protocol (stup) ? derived from the t7906 single point to point ieee 1 355 high speed controller ? known anomalies of the t7906 chip corrected ? host interface ? gives read/write accesses to the at7912f configura tion registers ? gives read/write accesses to the spacewire channel ? adc/ dac interface ? allows direct connection of an adc with a width of up to 16 bits ? allows direct connection of a dac with up to 16 da ta lines and the required control signals ? fifo interface ? ram interface ? 16-bit data bus and 16-bit address bus ? four chip selects to address 4 different memory pa rtitions ? two independent uart interfaces ? 24 bidirectional general purpose i/os ? two 32-bit timers / event counters ? spacewire link performance ? at 3.3v : 100mbit/s full duplex communication ? at 5v : 200mbit/s full duplex communication ? operating range ? voltages ? 3v to 3.6v ? 4.5v to 5.5v ? temperature ? - 55c to +125c ? maximum power consumption ? at 3.6v with a 5mhz clock: 150mw ? at 5.5v with a 5mhz clock: 700mw ? radiation performance ? total dose tested successfully up to 50 krad (si) ? no single event latchup below a let of 80 mev/mg/c m2 ? esd better than 2000v ? quality grades ? qml-q or v with smd ? package: 100pins mqfpf ? mass: 3grams single spacewire link high speed controller at7912f
2 7829a?aero?10/08 1. description the at7912f provides an interface between a spacewi re link according to the space- wire standard ecss-e-50-12a and several different i nterfaces. the at7912f was designed by eads astrium in germany under the name 'smcs116spw" for "scalable multi-channel communicat ion subsystem for space- wire". it is manufactured using the seu hardened c ell library from atmel mg2rt cmos 0.5m radiation tolerant sea of gates technolo gy. for any technical question relative to the function ality of the at7912f please contact atmel technical support at assp-applab.hotline@nto.atmel.com . this document should be read in conjunction with eads astrium 'smcs116spw user manual' . this user manual is available at www.atmel.com . a block diagram of the at7912f is given in figure 1 . figure 1. at7912f block diagram the at7912f provides one spacewire serial communica tion link with up to 200 mbit/s data transmit rate. it features a link disconnect d etection and parity check at character
3 7829a?aero?10/08 level as well as an additional checksum generation/ check at packet level. the at7912f supports both the standard spacewire link protocol (transparent mode) and the stup (serial transfer universal protocol) for efficient packet oriented data transfer. in addition to the serial spacewire link, the at791 2f provides several different interfaces: ? host interface ? adc interface ? dac interface ? ram interface ? fifo interface ? general purpose i/o ? uart interfaces ? timers / event counters ? jtag (ieee 1149.1) 2. pin configuration table 2-1. pin assignment pin number name pin number name pin number name pin number name 1 pllout 26 iob9 51 data4 76 tmr2_clk 2 gnd 27 vcc 52 data5 77 rxd1 3 vcc 28 gnd 53 data6 78 tmr1_exp 4 vcc 29 iob10 54 data7 79 tmr2_exp 5 ldo 30 iob11 55 data8 80 txd1 6 lso 31 iob12 56 vcc 81 hdata0 7 ldi 32 iob13 57 gnd 82 hdata1 8 lsi 33 iob14 58 data9 83 hdata2 9 gnd 34 iob15 59 data10 84 hdata3 10 tck 35 iob16 60 data11 85 hdata4 11 tms 36 iob17 61 vcc 86 hdata5 12 tdi 37 iob18 62 gnd 87 hdata6 13 trst* 38 iob19 63 data12 88 vcc 14 tdo 39 iob20 64 data13 89 gnd 15 gnd 40 iob21 65 data14 90 hdata7 16 vcc 41 iob22 66 data15 91 hdatnadr* 17 iob0 42 iob23 67 gpio0 92 hsel* 18 iob1 43 iob24 68 gpio1 93 hwrnrd 19 iob2 44 iob25 69 gpio2 94 hintr* 20 iob3 45 iob26 70 gpio3 95 reset* 21 iob4 46 iob27 71 gpio4 96 clk 22 iob5 47 data0 72 gpio5 97 vcc_3volt 23 iob6 48 data1 73 gpio6 98 gnd 24 iob7 49 data2 74 gpio7 99 gnd 25 iob8 50 data3 75 tmr1_clk 100 vcc
4 7829a?aero?10/08 3. pin description table 3-1. pin description signal name (1)(3) type (2)(4) function 5v 0.5v max. output current [ma] 3.3v 0.3v max. output current [ma] load [pf] hsel* i when low, the external host selects the at7912f hos t interface hwrnrd i host interface write/read signal if hwrnrd is high during hsel* low, the host writes data to the address register or to the at7912f registers. if hwrnrd is low during hsel* low, the host reads d ata from the address register or the at7912f registers. hdatnadr i host interface data/address signal if hdatnadr is high during read, the host reads/wri tes data from/to the internal at7912f (data) registers. if hdatnadr is low during read, the host reads/writes address from/to the address register. hdata(7:0) i/o/z at7912f data bus. hdata(7:0) can be used as gpio(2), if the host inte rface is disabled 3 1.5 50 hintr* o host interrupt request line 3 1.5 50 tmr1_clk i timer1 clock (max. 12.5 mhz) tmr1_exp o timer1 expired. asserted for one cycle if the value of counter1 is equal to the content of register tperio d1(3:0). 3 1.5 50 tmr2_clk i timer2 clock (max. 12.5 mhz) tmr2_exp o timer2 expired. asserted for one cycle if the value of counter2 is equal to the content of register tperio d2(3:0). 3 1.5 50 rxd1 i receive data to uart1 txd1 o transmit data from uart1 3 1.5 50 ldi i link data input lsi i link strobe input ldo o link data output 12 6 25 lso o link strobe output 12 6 25 data(15:0) i/o/z common at7912f data bus 3 1.5 25 gpio(7:0) i/o general purpose input/output lines 3 1.5 25 iob(21:0) i/o control bus. the at7912f controls the connected interface via th ese lines. 6 3 25 iob(24:22) iob27 i/o 3 1.5 25 iob(26:25) i trst* i test reset. resets the test state machine
5 7829a?aero?10/08 notes: 1. groups of pins represent busses where the h ighest number is the msb. 2. o = output; i = input; z = high impedance 3. (*) = active low signal 4. o/z = if using a configuration with two at7912fs these signals can directly be con- nected together (wiror) tck i test clock. provides an asynchronous clock for jtag boundary scan tms i test mode select. used to control the test state machine. this input should be left unconnected or tied to ground during normal op eration tdi i test data input. provides serial data for the boundary scan logic tdo o/z test data output. serial scan output of the boundary scan path 3 1.5 50 reset* i at7912f reset. sets the at7912f to a known state. this input must be asserted (low) at power-up. the minimum width of re set low is 2 cycles when clk is running clk i external clock input to at7912f (max. 5 mhz) pllout o output of internal pll. used to connect a network of external rc filter dev ices. vcc_3volt i pll control signal configure pll for 3.3v or 5v operation vcc = 5 volt: connect this signal with gnd vcc = 3.3 volt: connect this signal with vcc vcc power supply gnd ground table 3-1. pin description (continued) signal name (1)(3) type (2)(4) function 5v 0.5v max. output current [ma] 3.3v 0.3v max. output current [ma] load [pf]
6 7829a?aero?10/08 3.1 signals organization this section describes the signals of the at7912f. groups of signals represent buses where the highest number is the msb. figure 3-1. signals organization
7 7829a?aero?10/08 3.2 shared i/o some of the functions of the at7912f share the same i/o pins. this means that some functions are mutually exclusive. as an example, th e gpio port shares some of its i/o pins with the host interface. if the host interface is not used, these pins are available for gpio; otherwise they are used as the host address a nd data bus. the selection of which functions are being used is made by programmi ng the appropriate registers after a chip reset. a short overview of the signals allocation for the various functions is given in the table below. table 3-2. shared i/os description signal functions gpio i/o ram interface i/o fifo interface i/o dac/adc interface i/o uart & interrupts i/o hdata[7:0] gpio2[7:0] i/o gpio0 gpio0_0 i/o rts1* i gpio1 gpio0_1 i/o cts1* i gpio2 gpio0_2 i/o ext_irq0* i gpio3 gpio0_3 i/o ext_irq1* i gpio4 gpio0_4 i/o txd2 o gpio5 gpio0_5 i/o rxd2 i gpio6 gpio0_6 i/o rts2* o gpio7 gpio0_7 i/o rts2* i iob[7:0] gpio1[7:0] i/o ram_addr[7:0] o adc_addr[7:0] o iob8 ram_addr8 o adc_cs* o iob9 ram_addr9 o adc_r/c* o iob10 ram_addr10 o dac_wr* o iob11 ram_addr11 o dac_addr0 o iob12 ram_addr12 o dac_addr1 o iob13 ram_addr13 o dac_addr2 o iob14 ram_addr14 o fifo_trm_eop_ack o iob15 ram_addr15 o fifo_rcv_par fifo_eopl i/o iob16 ram_wr* o fifo_rcveop o iob17 ram_rd* o fifo_rcveep o iob18 ram_cs0* o fifo_rd* i/o iob19 ram_cs1* o fifo_wr* i/o iob20 ram_cs2* o fifo_empty* i/o
8 7829a?aero?10/08 iob21 ram_cs3* o fifo_full* i/o iob22 ram_test o adc_rdy i iob23 ram_tmr_rdy o adc_trig i iob24 ram_rcv_rdy o fifo_trmeop i iob25 ram_bus_req* i fifo_trmeep i iob26 ram_start_trm i fifo_rcv_eop_ack i iob27 ram_start_rcv i fifo_trm_par fifo_eoph i/o table 3-2. shared i/os description (continued) signal functions gpio i/o ram interface i/o fifo interface i/o dac/adc interface i/o uart & interrupts i/o
9 7829a?aero?10/08 4. interfaces the at7912f provides an interface between a spacewi re link according to the space- wire standard ecss-e-50-12a and several different i nterfaces: ? host interface ? adc/dac interface ? ram interface ? fifo interface ? general purpose i/o ? uart interfaces ? timers / event counters 4.1 host interface although the at7912f is primarily designed to be re motely controlled, it can neverthe- less be programmed and controlled by a local host i f required. for that purpose the host interface provides 8 multiplexed data and address l ines. 4.2 adc/dac interface the adc interface allows connecting an adc with a w idth of up to 16 bits directly to the at7912f. the ad conversion can be started by reques t via link or in a cyclic manner triggered by the on chip timers. when the ad conver sion is ready, this is recognized by an external signal like "ready" or by an internal t rigger, for example from the on chip timer. after reading the sample from the adc it is then sent over the link. an 8-bit address generator is provided to allow multiplexing of analog signals. the address gen- erator will start at a pre-programmed start address and will be incremented after each conversion. the dac interface is very similar to the adc interf ace. it provides up to 16 data lines and the required control signals. the data to be se nt to the dac is received from the link and is stored in a register until the command "star t dac" is received. after that com- mand the register values will be put to the dac. 4.3 ram interface the ram interface provides a 16-bit data bus and 16 -bit address bus. four chip select lines allow addressing four different memory partit ions (banks). this partitioning into dif- ferent banks is done using 4 internal address bound ary registers. these are 8 bit wide and provide a minimum page size of 1024 words. the memory interface can be pro- grammed to use 0 to 7 wait states.
10 7829a?aero?10/08 4.4 fifo interface the fifo (8-bit or 16-bit data width) interface pro vides the control signals full, write, empty and read, depending on the direction of the d ata flow (receive/transmit). data received from the fifo interface is sent over the spacewire link grouped in pack- ets. the length of a packet (in bytes) can be speci fied either by setting an internal counter or by external signals. this interface can be programmed to use 0 to 7 wait states. the fifo interface handles two operating modes: ? an active mode where the at7912f fifo controller r eads and writes from/to an external fifo ? a passive mode where an external controller reads and writes from/to the at7912f internal fifo. 4.5 gpio interface the general purpose i/o (gpio interface) provides u p to 24 bidirectional signal lines. the direction (input or output) of each gpio line c an be set individually via register. data to/from the gpio lines is written / read via t he gpio data register. the gpio pro- vides 8 dedicated i/o lines, the remaining 16 lines of the port are shared with the adc address and host data bus. these gpio lines are ava ilable when the corresponding unit (e.g. the host data bus) of the at7912f is not bein g used (disabled). 4.6 uart interface two independent uarts are included in the at7912f a s well. one uart uses dedi- cated i/o lines whereas the second uart is sharing its pins with the gpio port. the transmit rate of the uarts in bps can be programmed via a 12-bit wide register with a maximum bit rate of about 780 kbit/s. each uart has a 4-byte fifo in transmit, and a 4-by te fifo in receive direction. the uarts can optionally use hardware handshake (rt s/cts). 4.7 timers / event counter two 32-bit on-chip timers are available on the at79 12f. each timer provides a 32-bit counter and a 32-bit r eload register. the two timers can be operated independently or cascaded. the timers can be used to set an external signal wh en the timeout value is reached. each timer can generate periodic interrupts or only one interrupt, depending on configu- ration. an external output, tmr_exp, signals to oth er devices that the timer count has expired. an external input, tmr_clk, is provided wh ich can be used as trigger source for the timer.
11 7829a?aero?10/08 5. operating modes 5.1 configuration of the at7912f the at7912f provides registers and ports for config uration. each register contains exactly one byte (read / write), whereas a port (e. g. a fifo interface) behaves like a fifo, meaning that multiple data bytes can be read or written from/to the port. the ports of the at7912f such as the fifo, uart, ad c and ram interfaces are accessed by a read/write command to the correspondi ng port address. in the case of fifo, host, uart and memory interfaces, a packet or iented access is also possible (meaning transferring multiple data bytes with a si ngle command). the read/write selec- tion of a command is done by setting bit 7 (msb) of the first byte to one (read) or zero (write). all internal registers are 8-bit wide addressable. two simple commands, read and write, suffice to access all registers of the at7912f. configuration/programming of the at7912f internal r egisters is done via either a simple protocol over the spacewire link or stup over the s pacewire link or directly via the host interface. ? the simple protocol over the spacewire, compatible with the t7906 (scmcs116) link requires a command byte and, if necessary, one or more data bytes. the simple protocol ignores following bytes, if more bytes are sent. ? the stup over the spacewire link uses 4 bytes for commands. it also supports logical addressing. ? the host interface provides a direct access to the internal registers through a 8-bit multiplexed address/data bus. after reset, the host interface is enabled. after a chip reset the at7912f is configured via th e internal controller. this can be either by receiving the configuration data from the spacewire link or by an external con- troller connected to the host port of the at7912f.
12 7829a?aero?10/08 6. test interface 6.1 jtag this represents the boundary scan testing provision s specified by ieee standard 1149.1 of the joint testing action group (jtag). th e at7912f test access port and on- chip circuitry is fully compliant with the ieee 114 9.1 specification. the test access port enables boundary scan testing of circuitry connecte d to the at7912f i/o pins. 7. at7912f differences with thet7906e a few differences between the at7912f and the t7906 e exist in the registers, the sig- nals and the pinout. these differences are detailed in the section 15 of the ?smcs116spw user manual?.
13 7829a?aero?10/08 8. typical applications many applications require a spacewire link front en d, however, no controller is required on the unit. thanks to its communication memory int erface, the at7912f satisfies the requirements of these applications. due to its smal l package and low power consump- tion it is an excellent alternative to fpga based s olutions. a system using the at7912f as a communication front -end for a microcontroller is shown in the following figure: figure 8-1. processor interface additional application targets of the at7912f are m odules and units without any built-in communication features, such as special image compr ession chips, application specific programmable logic or mass memory. the at7912f is p erfectly suited to be used on "non intelligent" modules such as a/d converter or sensor interfaces, due to its "control by link" feature and system control facilities. in addition, its fault tolerance feature makes the device very interesting for many critical indus trial measurement and control systems. example applications of the at7912f as communicatio n and system controller on an interface node consisting of an adc and dac is give n in the figure below: figure 8-2. adc/dac interface
14 7829a?aero?10/08 9. pll filter the at7912f embeds a pll to generate its internal c lock reference. the pllout pin of the pll is the output of the at7912f that allows connection of the external filter of the pll. the following figure presents the connection o f the pll filter. figure 9-1. pll filter table 9-1. pll filter recommended components 10. power supply to achieve its fast cycle time, the at7912f is desi gned with high speed drivers on out- put pins. large peak currents may pass through a ci rcuit board's ground and power lines, especially when many output drivers are simu ltaneously charging or discharging their load capacitances. these transient currents c an cause disturbances on the power and ground lines. to minimize these effects, the at 7912f provides separate supply pins for its internal logic and for its external dr ivers. all gnd pins should have a low impedance path to gr ound. a ground plane is required in at7912f systems to reduce this impedance, minimi zing noise. the vcc pins should be bypassed to the ground plane using 8 high-frequency capaci- tors (0.1 f ceramic). keep each capacitor's lead a nd trace length to the pins as short as possible. this low inductive path provides the a t7912f with the peak currents required when its output drivers switch. the capaci tors' ground leads should also be short and connect directly to the ground plane. thi s provides a low impedance return path for the load capacitance of the at7912f output drivers. the following pins must have a capacitor: 3, 4, 16, 27, 56, 61, 88 and 100. r1 1,5 k 5%, ?w c1 22pf, 5% c2 1.8nf, 5% at7912f
15 7829a?aero?10/08 11. electrical characteristics 11.1 absolute maximum ratings table 11-1. absolute maximum ratings stresses above those listed may cause permanent dam age to the device. parameter symbol value unit supply voltage vcc -0.5 to +7 v i/o voltage -0.5 to vcc + 0.5 v operating temperature range (ambient) ta -55 to +125 c junction temperature tj 175 c storage temperature range tstg -65 to +150 c thermal resistance junction to case rthjc 5 c/w
16 7829a?aero?10/08 11.2 dc electrical characteristics the at7912f can work with vcc = + 5 v 0.5 v and v cc = + 3.3v 0.3v. although specified for ttl outputs, all at7912f outputs are cmos compatible and will drive to vcc and gnd assuming no dc loads. table 11-2. 5v operating range dc characteristics. notes: 1. applicable for hdata[7:0], hintr*, tmr1_exp , tmr2_exp, txd1, data[15:0], gpio[7:0], iob[24:22], iob27 and tdo pins 2. applicable for iob[21:0] pins 3. applicable for ldo and lso pins table 11-3. 3.3v operating range dc characteristics. notes: 1. applicable for hdata[7:0], hintr*, tmr1_exp , tmr2_exp, txd1, data[15:0], gpio[7:0], iob[24:22], iob27 and tdo pins 2. applicable for iob[21:0] pins 3. applicable for ldo and lso pins parameter symbol min. max. unit conditions operating voltage vcc 4.5 5.5 v input high voltage vih 2.2 v input low voltage vil 0.8 v output high voltage voh 2.4 v iol = 1.5, 3, 6ma / vcc = vcc(min) output low voltage vol 0.4 v ioh = 1, 2, 4ma / vcc = vc c(min) output short circuit current ios 90 (1) 180 (2) 270 (3) ma ma ma vout = vcc vout = gnd parameter symbol min. max. unit conditions operating voltage vcc 3.0 3.6 v input high voltage vih 2.0 v input low voltage vil 0.8 v output high voltage voh 2.4 v iol = 3, 6, 12ma / vcc = vcc(min) output low voltage vol 0.4 v ioh = 3, 6, 12ma / vcc = v cc(min) output short circuit current ios 50 (1) 100 (2) 155 (3 ma ma ma vout = vcc vout = gnd
17 7829a?aero?10/08 11.3 power consumption maximum power consumption figures at vcc = 5.5v; -5 5c; clk = 5 mhz are presented in the following table. table 11-4. 5v power consumption maximum power consumption figures at vcc = 3.6v; -5 5c; clk = 5 mhz are presented in the following table. table 11-5. 3.3v power consumption operation mode power consumption [ma] not clocked 2 at7912f in reset 22 at7912f in idle (1) 1. idle means clk = 5 mhz, link started and running at 10mbit/s, no activity on the other interfaces. 75 maximum 120 operation mode power consumption [ma] not clocked 1 at7912f in reset 10 at7912f in idle (1) 1. idle means clk = 5 mhz, link started and running at 10mbit/s, no activity on the other interfaces. 23 maximum 40
18 7829a?aero?10/08 11.4 ac electrical characteristics the following table gives the worst case timings me asured by atmel on the 4.5v to 5.5v operating range table 11-6. 5v operating range timings. the following table gives the worst case timings me asured by atmel on the 3.0v to 3.6v operating range table 11-7. 3.3v operating range timings for guaranteed timings on the two operating voltage ranges, refer to the section 12 of the ?smcs116spw user manual? parameter symbol min. max. unit propagation delay tck low to tdo low tp1 20 ns propagation delay clk high to tmr1_exp low tp2 23 ns propagation delay clk high to ldo low tp3 16 ns propagation delay clk high to hintr* low tp4 25 ns propagation delay clk high to iob18 low tp5 16 ns parameter symbol min. max. unit propagation delay tck low to tdo low tp1 33 ns propagation delay clk high to tmr1_exp low tp2 38 ns propagation delay clk high to ldo low tp3 27 ns propagation delay clk high to hintr* low tp4 41 ns propagation delay clk high to iob18 low tp5 27 ns
19 7829a?aero?10/08 12. package drawings 12.1 mqfpf100 100 pins ceramic quad flat pack (mqfpf 100) * lid is connected to ground.
20 7829a?aero?10/08 13. ordering information part-number temperature range package quality flow at7912fkf-e 25c mqfpf100 engineering sample 5962_08a0202qxc -55c to +125c mqfpf100 qml_q 5962_08a0202vxc -55c to +125c mqfpf100 qml_v
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